IEEE Micro

PrePrint: A Benchmark Characterization of the EEMBC Benchmark Suite

Benchmarking is as much a science as it is an art, and at times involves a leap of faith for the benchmark consumers. Most people trust provided benchmark suites to be complete, accurate, and consistent. By default, when comparing one processor to another, the benchmark scores are the authority used as a relative measure of performance. Rarely do the benchmark consumers understand or verify the underlying stresses that the benchmarks place on the processors. This study unmasks the stress points of the popular embedded benchmark suite, the EDN Embedded Microprocessor Benchmark Consortium Suite (EEMBC), using the technique of Benchmark Characterization (BC).

IEEE Micro - September/October 2009 (Vol. 29, No. 5)

IEEE Micro

PrePrint: Hardware Software Codesign for High-speed Signature-based Virus Scanning

It is a trend to offload signature matching to a hardware engine for high-speed network content security applications. Most existing research works claim the achieved high throughput of the hardware engine only, but it is also significant to study the reasons behind the gap between the throughput of an integrated system and that of the hardware engine alone. We examine this issue by offloading virus scanning in ClamAV to a hardware engine BFAST*. Although the ideal throughput is 8.79 Gbps in the hardware simulation, the bus clock and launching scanning in each batch of data degrade the throughput to 3.01 Gbps, even if the DMA were infinitely fast and the data is already in the DMA buffer. The DMA speed in our platform is also a bottleneck, further degrading the throughput to 912.7 Mbps. The overall throughput of the system is only 151 Mbps, due to copying data from the user space into the DMA buffer. Transferring data from the user space into BFAST* takes about 90% of the total time. From the observations, we can tell how large the performance can be improved in each execution stage, if a solution is devised, e.g., a faster DMA or kernel-level scanning.

PrePrint: Coherency Hub Design for Multi-socket Sun Servers with CoolThreads (TM) Technology

This paper describes the micro-architecture of a Coherency Hub (CoHub) ASIC for a 4-socket highly-threaded multiprocessor using Sun's UltraSPARC ® T2 Plus processor. UltraSPARC T2 Plus is an 8-core CMT processor in the Sun Servers with CoolThreadsTM Technology family. CoHub enables cost-effective scaling to 4 nodes with a total thread count of 256 and near-linear performance scaling on transaction processing workloads. Extending a 2-node “glueless” system to a 4-node system without processor changes was a key requirement. CoHub broadcasts snoop requests, serializes requests to the same address, and consolidates snoop responses. It communicates with nodes via serial links, using a proprietary link layer implemented over FBDIMM. We present the coherency scheme, ASIC design, transaction flows, and engineering challenges created by 800 MHz operation and 6-stage pipeline budget. We report performance scalability results measured on commercial server benchmarks.