IEEE Design and Test of Computers

Special Issue on High-Level Synthesis

Interconnect challenges in the multicore era

Staff listing

ITC 2008 Highlights

Guest Editors' Introduction: Tackling Key Problems in NoCs

COSI: A Framework for the Design of Interconnection Networks

Editor's note:This article presents a software framework for communication infrastructure synthesis of distributed systems, which is critical for overall system performance in communication-based design. Particular emphasis is given to on-chip interconnect synthesis of multicore designs.—Radu Marculescu, Carnegie Mellon University

A Quality-Driven Design Approach for NoCs

Editor's note:This article advocates a systematic approach to improve NoC design quality by guiding architectural choices according to the difficulty of verification and test. The authors propose early quality metrics for added test, monitoring, and debug hardware.—Yatin Hoskote, Intel

Characterization of Equalized and Repeated Interconnects for NoC Applications

Editor's note:As the number of cores increases and on- and off-chip bandwidth demand rises, it is becoming increasingly more difficult to rely on conventional interconnects and remain within the chip power budget. This article explores leveraging equalization for global and semi-global long interconnects to overcome this problem.—Li-Shiuan Peh, Princeton University

An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC

Editor's note:The diversification of the SoC market has increased the need for domain-specific programmable platforms that can be tailored to postfabrication products. This article presents a design case study on the interconnect for such a programmable platform, as part of the Morpheus project.—Li-Shiuan Peh, Princeton University

Signal Integrity Enhancement in Digital Circuits

This article proposes a new methodology for enhancing SoC signal integrity without degrading performance in the presence of power-ground voltage transients. The underlying principle is the dynamic adaptation of the clock duty cycle to propagation delay variation along disturbed logic paths. This methodology makes digital circuits more robust to power line fluctuations while maintaining the at-speed clock rate.

Hardware-Software Approaches to In-Circuit Emulation for Embedded Processors

In-circuit emulators have become part of the permanent structure of microprocessor cores to support on-chip test and debug activities in highly integrated environments such as SoCs. However, ICE design styles and operation principles are quite diverse. This article presents a taxonomy based on the notions of foreground and background operations and hardware-software implementation alternatives to organize existing in-circuit emulation approaches.

Verification of Pin-Accurate Port Connections

Before verifying the functionality of SoCs, designers must ensure the correctness of the pin-accurate interfaces of up to hundreds of integrated IP blocks. This article presents a new connection model and a corresponding error model for pin-accurate port connections, along with an algorithm for generating the minimum pattern set, a methodology for diagnosing errors, and a port connection verification flow.

Designing Micro- and Nanosystems for a Safer and Healthier Tomorrow

Adapting to the times

CEDA Currents

OCP-IP NoC Benchmarking WG activities