IEEE Design and Test of Computers

PrePrint: Modeling Low-K Dielectric Breakdown in the Presence of Multiple Feature Geometries and Die-to-Die Linewidth Variation

Backend geometries on chips contain a wide variety of features. This paper analyzes data from test structures implemented on a 45nm technology test chip to relate geometry to failure rate statistics for low-k dielectric breakdown. An area scaling model is constructed which accounts for the presence of die-to-die linewidth variation, and a methodology is proposed to determine if low-k materials satisfy lifetime requirements in the presence of die-to-die linewidth variation.

PrePrint: Multi-Dimensional Test Escape Rate Modeling

The Williams and Brown Model has long been the gold standard for estimating test escape rate as a function of yield and fault coverage for a single test type. However, the designs for system on chip (SoC) today are composed of many different types of circuitry, each with a number of varying test types. The tests in turn frequently manifest overlapping failing unit detections. This paper details the development of an empirical methodology which permits test escape rate estimation and comprehends multiple overlapping test types and coverages.

PrePrint: Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained

For sub-65nm design, there can be many timing effects not explicitly and/or accurately modeled and simulated, resulting in unexpected timing mismatch between simulated timing behavior and observed timing behavior on silicon chips. For diagnosing timing mismatch, this paper describes a diagnosis approach that analyzes and ranks potential design related issues. We explain in detail how one should use diverse "features" to encode the potential design issues and how features can be interpreted properly by various kernel functions in a data learning algorithm for analyzing the mismatch. Then, we explain how kernel-based learning can be used to rank the importance of features such that a feature contributing the most to the timing mismatch is ranked the highest. We conclude the paper by showing simulated experimental results based on an industrial ASIC design.

IEEE Design and Test of Computers - September/October 2009 (Vol. 26, No. 5)

IEEE Design and Test of Computers

PrePrint: Accelerating Emulation and Providing Full Chip Observability and Controllability at Run-Time

Performing hardware emulation on FPGAs is a significantly faster and more accurate approach for the verification of complex designs than software simulation. Therefore, hardware Simulation Accelerator and Emulator co-processor units are used to offload calculation-intensive tasks from the software simulator. However, the communication overhead between the software simulator and the hardware emulator is becoming a new critical bottleneck. Moreover, in a hardware emulation environment it is impossible to bring outside of the chip a large number of internal signals for verification purposes. Therefore, on-chip observability has become a significant issue. In our work we tackle both aforementioned problems. First, we deploy a novel emulation framework that automatically transforms into synthesizable code certain HDL parts of the testbench, in order to offload them from the software simulator and, more importantly, minimize the aforementioned communication overhead. Next, we extend this architecture by adding multiple fast scan-chain paths in the design in order to provide full circuit observability and controllability on the fly. In this paper, we briefly describe our approach for reducing the communication overhead problem, and present, for the first time, our complete innovative system which offers extensive observability and controllability in complex Design Under Tests (DUTs).