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		<title>TechOnLine.com - Feature Articles</title>
		<link>http://www.techonline.com</link>
		<description>The latest electronics engineering technical articles and commentaries exclusive to TechOnLine</description>
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		<copyright>Copyright 2008 TechInsights, a Division of United Business Media LLC. All rights reserved.</copyright>
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			<title><![CDATA[A Formal Methods-based verification  approach to medical device software analysis]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=284150a9582aaf8b82f6684d875246af]]></link>
			<pheedo:origLink>http://www.embedded.com/showArticle.jhtml?articleID=222700533</pheedo:origLink>
			<description><![CDATA[How to use formal methods&quot;based abstract interpretation techniques to mathematically prove the absence of a defined set of run-time errors and a comparison with techniques as code review, static analysis, and dynamic testing.<br clear="both" style="clear: both;"/>
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			<title><![CDATA[Reducing Costs, Risks, Time to Market with Virtualized Systems Development]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=622b29f4258dd665eb17e71c6a937edd]]></link>
			<pheedo:origLink>http://www.edadesignline.com/howto/222700451</pheedo:origLink>
			<description><![CDATA[To achieve developer efficiency and software quality with virtual system development tools, it is necessary to use a fully-featured simulation infrastructure with the ability to create custom models.<br clear="both" style="clear: both;"/>
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			<title><![CDATA[Reducing Costs, Risks, Time to Market with Virtualized Systems Development]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=9523a89ca30b2a9452076eee6b9bbe2a]]></link>
			<pheedo:origLink>http://www.embedded.com/showArticle.jhtml?articleID=222700419</pheedo:origLink>
			<description><![CDATA[To achieve developer efficiency and software quality with virtual system development tools, it is necessary to use a fully-featured simulation infrastructure with the ability to create custom models.<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
  <a style='font-size: 10px; color: maroon;' href='http://www.pheedcontent.com/hostedMorselClick.php?hfmm=v3:70aea4c965219d69ce22c4c43bfd9fcd:aEdvvZyg3OSJkMvjz8HxmJ4y11jkJIpvgqNAS3CsL10vGojfaHdqnka7HQ%2FE8RRp1okt8RhteFZg'><img border='0' title='Email this Article' alt='Email this Article' src='http://images.pheedo.com/images/mm/emailthis.png'/></a>
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			<title><![CDATA[Hardware Testing]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=c2eb41146d46dcacabd9710309a850b8]]></link>
			<pheedo:origLink>http://www.embedded.com/showArticle.jhtml?articleID=222700336</pheedo:origLink>
			<description><![CDATA[Board testing is harder than you think, but there are solutions<br clear="both" style="clear: both;"/>
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			<title><![CDATA[Motor control in air conditioners with dual sensor less FOC and active PFC]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=f01b7f5f057f546f5f464bb2ca85f483]]></link>
			<pheedo:origLink>http://www.industrialcontroldesignline.com/howto/222700359</pheedo:origLink>
			<description><![CDATA[Improved energy efficiency and reduced system costs are the driving factors in modern motor control designs. Sophisticated motor control concepts with sensor less Field Oriented Control (FOC) and Power Factor Correction (PFC) help to fulfill these demands. The article shows how these concepts can be used in an air conditioner design for vehicles. <br clear="both" style="clear: both;"/>
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			<title><![CDATA[Motor control in air conditioners with dual sensor less FOC and active PFC]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=d1b1a641a75e81fc3a4de563325447eb]]></link>
			<pheedo:origLink>http://www.embedded.com/showArticle.jhtml?articleID=222700339</pheedo:origLink>
			<description><![CDATA[Improved energy efficiency and reduced system costs are the driving factors in modern motor control designs. Sophisticated motor control concepts with sensor less Field Oriented Control (FOC) and Power Factor Correction (PFC) help to fulfill these demands. The article shows how these concepts can be used in an air conditioner design for vehicles. <br clear="both" style="clear: both;"/>
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			<title><![CDATA[Time domain modeling and simulation of Intel QuickPath interconnect circuits (Part 1 of 3)]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=8b53d67abac60cccd112cd085caba178]]></link>
			<pheedo:origLink>http://www.edadesignline.com/howto/222700452</pheedo:origLink>
			<description><![CDATA[This article explores and explains key issues related to modeling and simulation in this interconnect scheme, but its lessons apply to other designs as well<br clear="both" style="clear: both;"/>
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			<title><![CDATA[Presented By:]]></title>
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			<guid isPermaLink="false">8b53d67abac60cccd112cd085caba178</guid>
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			<title><![CDATA[ZigBee RF4CE coexistence with common 2.4-GHz ISM-band consumer electronics]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=e8c1816a0ae04776481e9bf60be6dc28]]></link>
			<pheedo:origLink>http://www.embedded.com/showArticle.jhtml?articleID=222700329</pheedo:origLink>
			<description><![CDATA[Understand the challenges and tradeoffs when using this slice of spectrum, crowded with devices supporting different standards<br clear="both" style="clear: both;"/>
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			<title><![CDATA[Presented By:]]></title>
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			<title><![CDATA[Power Tip 20: Watch Those Unintended Resonant Responses ]]></title>
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			<pheedo:origLink>http://www.powermanagementdesignline.com/howto/222601016</pheedo:origLink>
			<description><![CDATA[Understand how filter ringing can lead to power-supply failures
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			<title><![CDATA[Watch Those Unintended Resonant Responses ]]></title>
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			<pheedo:origLink>http://www.embedded.com/showArticle.jhtml?articleID=222700337</pheedo:origLink>
			<description><![CDATA[Understand how filter ringing can lead to power-supply failures<br clear="both" style="clear: both;"/>
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			<title><![CDATA[Looking ahead: Data converter trends for 2010]]></title>
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			<pheedo:origLink>http://www.embedded.com/showArticle.jhtml?articleID=222700340</pheedo:origLink>
			<description><![CDATA[Converters are key to mixed-signal products; here's a perspective  on where they are headed in terms of performance, power, and functionality. . . . <br clear="both" style="clear: both;"/>
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			<title><![CDATA[&quot;Also of Interest&quot; and &quot;Elementals&quot; for February 8, 2010; plus recent &quot;Planet Analog&quot; Newsletters]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=0292e1443b693f84668e903128717315]]></link>
			<pheedo:origLink>http://www.planetanalog.com/features/showArticle.jhtml?articleID=222601028</pheedo:origLink>
			<description><![CDATA[Check out these interesting and tutorial items from other engineering and design publications, courtesy of &lt;i&gt;Planet Analog&lt;/i&gt;, as well as an archive of the &lt;i&gt;Planet Analog&lt;/i&gt; Newsletter
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			<title><![CDATA[Making packet processing more efficient with network-optimized multicore designs: Part 2]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=1f3f22cede274827e58c501e1e15b3c0]]></link>
			<pheedo:origLink>http://www.edadesignline.com/howto/222700219</pheedo:origLink>
			<description><![CDATA[In terms of both power consumption, it is now feasible to build complete network packet processing designs using general purpose architecture processors, rather than dedicated ASIC and ASSP SoCs optimized for the application. Part 2: Minimizing/hiding latency.<br clear="both" style="clear: both;"/>
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			<title><![CDATA[Making packet processing more efficient with network-optimized multicore designs: Part 2]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=60a68f1a7d139fe109c284f03c9d264e]]></link>
			<pheedo:origLink>http://www.embedded.com/showArticle.jhtml?articleID=222700180</pheedo:origLink>
			<description><![CDATA[In terms of both power consumption, it is now feasible to build complete network packet processing designs using general purpose architecture processors, rather than dedicated ASIC and ASSP SoCs optimized for the application. Part 2: Minimizing/hiding latency.<br clear="both" style="clear: both;"/>
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			<title><![CDATA[Managing Complex SoC verification using plan based verification techniques]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=2aef248833730093f2fde0d047ea90c8]]></link>
			<pheedo:origLink>http://www.edadesignline.com/howto/222700069</pheedo:origLink>
			<description><![CDATA[Meeting the quality requirements of a complex SoC requires managing large verification projects. In this article, Freescale and STMicroelectronics recount a recent experience with a verification management solution (Incisive Enterprise Manager) from Cadence, for the verification of a 32-bit microcontroller project for the automotive industry.<br clear="both" style="clear: both;"/>
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