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		<title>Programmable Logic DesignLine</title>
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		<description></description>
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		<copyright>Copyright &amp;copy; 2008 TechInsights, a Division of United Business Media LLC. All rights reserved.</copyright>
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			<title>Programmable Logic DesignLine</title>
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			<title><![CDATA[Viewpoint: Your future is programmable]]></title>
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			<pheedo:origLink>http://www.pldesignline.com/223500006?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[The state of the electronics industry today, and certainly in the future, directly challenges that traditional view of technology-focused product design evolution.<br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 10 Mar 2010 16:11:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
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			<title><![CDATA[Lattice claims 200 million ispMACH 4000 CPLDs shipped]]></title>
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			<description><![CDATA[Lattice Semiconductor said it has now shipped more than 200 million ispMACH 4000 complex programmable logic devices.<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 10 Mar 2010 15:55:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
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			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Wed, 10 Mar 2010 15:55:00 EST</pubDate>
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			<title><![CDATA[Stratix IV passes Interlaken device interoperability testing ]]></title>
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			<description><![CDATA[Altera said its Stratix IV FPGAs passed the Interlaken Alliance's device interoperability testing, certifying that its FPGAs interface with third-party components using the Interlaken protocol. <br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 10 Mar 2010 15:26:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
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			<title><![CDATA[RTOS vendor announces support for Actel's SmartFusion]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=35659d9bfd9f2035aa3b4aefdfc5158e]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223400088?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[Embedded software component provider Micrium announced that it has successfully ported its 
uC/OS-II and uC/OS-III kernels and uC/TCP-IP stack to Actel SmartFusion mixed-signal FPGA. <br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 10 Mar 2010 14:23:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
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			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Wed, 10 Mar 2010 14:23:00 EST</pubDate>
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			<title><![CDATA[What's your take on Actel's SmartFusion? ]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=d194fed7a0ef4cbc208120ed1c5f4a98]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223400085?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[After getting some pretty good responses to a request for perspectives on Tabula, we are going to the well again to ask for reader responses to Actel's new SmartFusion family.<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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<!-- foo -->]]></description>
			<pubDate>Wed, 10 Mar 2010 13:57:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[FPGA startup: Process tech eases ASIC migration]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=29a05aabbbc5e3603cc8eae06c6a5fc2]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223400079?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[A little more than a week after long-simmering programmable logic startup Tabula emerged from stealth mode, Tier Logic stepped into the light to offer the first details about its technology, which employs a novel processing change to build FPGA and ASIC products on a single die.  <br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 10 Mar 2010 11:01:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
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			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Wed, 10 Mar 2010 11:01:00 EST</pubDate>
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			<title><![CDATA[Interview with Chuck Thacker, PC pioneer]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=92863ccc62955b8d41edb1b44d35cac6]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223400082?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[Charles Thacker won the 2009 Turing Award for his work in the early 1970's on the Xerox PARC Alto, a forerunner of the Apple Macintosh and IBM PC, and is now a Microsoft researcher testing out parallel programming concepts on a multi-core FPGA development system he designed.<br clear="both" style="clear: both;"/>
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<!-- foo -->]]></description>
			<pubDate>Tue, 9 Mar 2010 16:19:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
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		<item>
			<title><![CDATA[Jim Hogan joins GateRocket advisory board]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=390a70a1bb3ef171d73f9e4be9fe067b]]></link>
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			<description><![CDATA[FPGA verification and debug software vendor GateRocket Inc. announced veteran EDA investor Jim Hogan has joined its advisory board. <br clear="both" style="clear: both;"/>
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			<pubDate>Tue, 9 Mar 2010 04:46:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
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		<item>
			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Tue, 9 Mar 2010 04:46:00 EST</pubDate>
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		<item>
			<title><![CDATA[IC Insights boosts 2010 chip growth forecast to 27%]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=4d6ac1d91aef9ac01397f3d007c40006]]></link>
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			<description><![CDATA[Market research firm IC Insights increased its estimate for 2010 semiconductor growth, saying it now expects chip revenue to increase 27 percent this year, reaching $253 billion. <br clear="both" style="clear: both;"/>
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			<pubDate>Mon, 8 Mar 2010 21:00:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
			<link>http://ads.pheedo.com/click.phdo?s=4d6ac1d91aef9ac01397f3d007c40006&amp;p=4</link>
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			<pubDate>Mon, 8 Mar 2010 21:00:00 EST</pubDate>
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		<item>
			<title><![CDATA[Analysts cite five opportunities in mobile data]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=96a55a10f3ffe4524c76868c55e5ddfb]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223200133?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[Systems and semiconductor companies have a handful of opportunities for growth in mobile data networks despite the fact most carriers will keep a lid on capital equipment spending over the next two years, according to analysts from Barclays Capital.<br clear="both" style="clear: both;"/>
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<!-- foo -->]]></description>
			<pubDate>Mon, 8 Mar 2010 12:16:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Viewpoint: The importance of FPGA-to-ASIC solutions to accelerate CPU-based protocols]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=dfd80bd2eeca770d2d827312d4d8bf45]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223101434?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[Joe Rash of CebaTech argues for protocol acceleration solutions, which leverage the capabilities afforded by FPGAs, to help customers get to market fast and capture market opportunities.<br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 3 Mar 2010 17:56:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Wed, 3 Mar 2010 17:56:00 EST</pubDate>
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			<title><![CDATA[Altera, Lattice Semi raise Q1 sales targets]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=b0af4ec2da4d6637b98cd4ed3c32dac2]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223101437?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[Programmable logic vendors Altera and Lattice Semiconductor increased their first quarter sales targets, citing better-than-expected growth across a broad range of products and market segments. <br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 3 Mar 2010 17:47:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Altera unveils safety data package for automation]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=cfe263c69f5ad1cd8ade354ed35fbb73]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223101409?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[Altera announced an industrial safety data package for automation applications at the Embedded World tradeshow.<br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 3 Mar 2010 15:57:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Xilinx rolls automotive Spartan-6, app kits ]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=ce3d9f55a1ccd2d85949fffbff9ece99]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223101382?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[At the Embedded World 2010 conference in Nuremberg, Germany, this week, Xilinx Inc. introduced a new family of Spartan-6 FPGAs optimized for automotive applications and Spartan-6 application development kits for video processing and industrial Ethernet around its targeted design platforms strategy. <br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 3 Mar 2010 14:03:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
			<link>http://ads.pheedo.com/click.phdo?s=ce3d9f55a1ccd2d85949fffbff9ece99&amp;p=4</link>
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			<pubDate>Wed, 3 Mar 2010 14:03:00 EST</pubDate>
		</item>
		<item>
			<title><![CDATA[Xilinx cutting distributor, changing strategy ]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=de718d90f7465247e88b2a6f5c49ef89]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223101371?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[Market-leading programmable logic vendor Xilinx will terminate its 23-year relationship with electronics distributor Nu Horizons Electronics effective June 5 due to a change in Xilinx' distribution strategy, according to a statement issued by Nu Horizons. <br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 3 Mar 2010 02:33:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Altera: Industry faces 'platform collision']]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=a3aa6aa61381dc01103becef157836ff]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223101370?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[Bradley Howe, vice president of IC engineering at Altera, said during a presentation that IC integration, while reducing the cost of systems, is creating a new and competitive environment. <br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Tue, 2 Mar 2010 17:42:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Semico: Good times are here for ICs]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=bcd340a098477e5a4e3e16b0af8169e7]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223101272?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[Good times are here for the IC industry, according to Jim Feldhan, president of Semico Research, who predicts a two-year growth cycle for ICs.<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Tue, 2 Mar 2010 12:05:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
			<link>http://ads.pheedo.com/click.phdo?s=bcd340a098477e5a4e3e16b0af8169e7&amp;p=4</link>
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			<pubDate>Tue, 2 Mar 2010 12:05:00 EST</pubDate>
		</item>
		<item>
			<title><![CDATA[Xilinx, Inova team on in-car video links]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=0be1a5f7ff5558062646f96a0418c1be]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223101269?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[Xilinx Inc. and Inova Semiconductors GmbH have introduced a communications transceiver design called Automotive Pixel Link (APIX) that can be deployed on the Xilinx Automotive (XA) family of Spartan-6 field programmable gate arrays (FPGAs). <br clear="both" style="clear: both;"/>
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<!-- foo -->]]></description>
			<pubDate>Tue, 2 Mar 2010 04:53:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Actel rolls mixed-signal FPGA with hard ARM core]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=7f18ee68c1a48a87b535ae009acb75bb]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223101270?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[Claiming a major breakthrough that could have broad appeal for embedded designers, Actel has introduced a family of flash-based FPGAs that feature a complete microcontroller subsystem built around a hard ARM Cortex-M3 processor and programmable analog blocks. <br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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<!-- foo -->]]></description>
			<pubDate>Tue, 2 Mar 2010 03:01:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[What's Your Take on Tabula? ]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=5ce7bb914100aaded19b795dbac5ae4a]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223101061?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[On paper, Tabula seems like a surefire winner. But I'm asking programmable logic users to share their thoughts on the startup and its newly announced  technology. <br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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<!-- foo -->]]></description>
			<pubDate>Mon, 1 Mar 2010 16:04:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
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			<description><![CDATA[<a href="http://ads.pheedo.com/click.phdo?s=5ce7bb914100aaded19b795dbac5ae4a&amp;p=4"><img alt="" style="border: 0;" border="0" src="http://ads.pheedo.com/img.phdo?s=5ce7bb914100aaded19b795dbac5ae4a&amp;p=4"/></a>]]></description>
			<pubDate>Mon, 1 Mar 2010 16:04:00 EST</pubDate>
		</item>
		<item>
			<title><![CDATA[3-D architecture promises new type of PLD]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=1243261c76cfb63a9014cb601bf9bc4a]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223101035?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[Startup Tabula made public details about its three-dimensional programmable logic architecture, which the company says will enable a new class of devices, 3PLDs, that offer the capability of an ASIC, ease of use of an FPGA and price points suitable for volume production.<br clear="both" style="clear: both;"/>
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<!-- foo -->]]></description>
			<pubDate>Mon, 1 Mar 2010 06:01:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Dodging Amdahl's Law with message passing, FPGA-based, parallel processing]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=ba0e2e0a1521e1a7d22fa8284865f3cd]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223100619?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[The debate continues about the right ratio of microprocessors to co-processors for large-scale parallel processing arrays. But most agree that the basic plumbing of memory management can be the real bottleneck. Today the only real solution is the microprocessor and co-processors sharing memory on the node, and then interconnecting many nodes with a GigE, Infiniband, or a custom interconnect configuring the nodes in a distributed memory layout.<br clear="both" style="clear: both;"/>
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<!-- foo -->]]></description>
			<pubDate>Wed, 24 Feb 2010 16:02:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Impulse C adds support for C-language math.h functions]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=897781a1dea10cd38f2560c217a4f0ab]]></link>
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			<description><![CDATA[Impulse Accelerated Technologies announced a new FPGA hardware library supporting C-language math.h functions.<br clear="both" style="clear: both;"/>
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<!-- foo -->]]></description>
			<pubDate>Wed, 24 Feb 2010 15:47:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Altera moves 40-nm Arria II GX to mass production]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=e4ad11c79f26a2292dba2e2c1b876fcb]]></link>
			<pheedo:origLink>http://www.pldesignline.com/223100567?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[Altera announced it is shipping in volume production the first members of its 40nm Arria II GX FPGA family specifically targeting 3-Gbps transceiver applications<br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 24 Feb 2010 04:00:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
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			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Wed, 24 Feb 2010 04:00:00 EST</pubDate>
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			<title><![CDATA[XMOS offers iPhone/iPod dock reference design]]></title>
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			<pheedo:origLink>http://www.pldesignline.com/223100579?cid=RSSfeed_programmablelogicdesignline_pldlRSS</pheedo:origLink>
			<description><![CDATA[An iPhone/iPod dock reference design from XMOS eliminates analog audio processing components, reducing RF interference and enabling bit-perfect digital audio for highest fidelity audio performance.<br clear="both" style="clear: both;"/>
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			<pubDate>Tue, 23 Feb 2010 09:30:00 EST</pubDate>
			<category>Programmable Logic DesignLine</category>
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