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		<title>EDA DesignLine</title>
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			<title><![CDATA[Synopsys discreetly acquires Gemini ]]></title>
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			<description><![CDATA[No news announcement. No press release. Yet, Synopsys Inc. has acquired Gemini Design Automation (Fremont, Calif.), a start-up company focused on the challenges of verifying complex analog and mixed-signal designs. <br clear="both" style="clear: both;"/>
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			<pubDate>Thu, 11 Mar 2010 09:48:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[TowerJazz joins IPL Alliance ]]></title>
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			<description><![CDATA[Foundry vendor TowerJazz Semiconductor Ltd. (Migdal Haemek, Israel) announced it has joined the IPL Alliance, an organization chartered with establishing an interoperable process design kit (PDK). <br clear="both" style="clear: both;"/>
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			<pubDate>Thu, 11 Mar 2010 09:37:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Thu, 11 Mar 2010 09:37:00 EST</pubDate>
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			<title><![CDATA[Evatronix to host technical 8051, USB seminars in Asia ]]></title>
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			<description><![CDATA[For those who use digital IP in the chip design process and wish to get faster to market with their SoC, Evatronix SA (Bielsko-Biala/Poland) has scheduled two free technical seminars on two popular IP technologies in the semiconductor industry &amp;#151;8051 and USB&amp;#151; in Beijing, China, and Hsinchu, Taiwan. <br clear="both" style="clear: both;"/>
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			<pubDate>Thu, 11 Mar 2010 05:15:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Thu, 11 Mar 2010 05:15:00 EST</pubDate>
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			<title><![CDATA[Viewpoint: Your future is programmable]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=bc239d1991f73d2e2844251722983902]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223500024?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[The state of the electronics industry today, and certainly in the future, directly challenges that traditional view of technology-focused product design evolution.<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 10 Mar 2010 16:11:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[Stratix IV passes Interlaken device interoperability testing ]]></title>
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			<pheedo:origLink>http://www.edadesignline.com/223500025?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Altera said its Stratix IV FPGAs passed the Interlaken Alliance's device interoperability testing, certifying that its FPGAs interface with third-party components using the Interlaken protocol. <br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 10 Mar 2010 15:26:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Wed, 10 Mar 2010 15:26:00 EST</pubDate>
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			<title><![CDATA[FPGA startup: Process tech eases ASIC migration]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=5b773cdb70c2a1dda683b3b0edfb6c93]]></link>
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			<description><![CDATA[A little more than a week after long-simmering programmable logic startup Tabula emerged from stealth mode, Tier Logic stepped into the light to offer the first details about its technology, which employs a novel processing change to build FPGA and ASIC products on a single die.  <br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 10 Mar 2010 11:01:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[ICE debugging: The end of the battleship game]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=8f198aa8435756fa648654e650828a43]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222900187?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Lauro Rizzatti at EVE-USA explains why the &quot;Battleship Game&quot; reminds him of trying to debug a system-on-chip (SoC) design using the in-circuit-emulation (ICE) mode.<br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 10 Mar 2010 09:07:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Wed, 10 Mar 2010 09:07:00 EST</pubDate>
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		<item>
			<title><![CDATA[Magma readies static timing analysis platform]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=337f0a0a737fc5479f60af0d9312d9a5]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223400014?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Magma Design Automation Inc. has introduced the Tekton timing analysis platform that is claimed to deliver fast multi-scenario analysis on a single CPU.
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			<pubDate>Wed, 10 Mar 2010 09:00:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Magma releases alternative to Monte Carlo analysis]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=3798fc91a3243470391d36bb339e2111]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223400004?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Magma Design Automation Inc. claimed its FineSim Fast Monte Carlo statistical simulation method delivers superior accuracy and up to 100 times speed improvement over traditional Monte Carlo analysis. <br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 10 Mar 2010 09:00:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Wed, 10 Mar 2010 09:00:00 EST</pubDate>
		</item>
		<item>
			<title><![CDATA[Getting disciplined about embedded software development: Part 3 - The value of postmortems]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=bb0308c0a111d118f81d0d48111620c4]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223400003?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Here's a guide from Jack Ganssle on doing software development in a disciplined way to reduce both errors and the time it takes to complete a project. Part 3: The value of postmortems<br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 10 Mar 2010 00:33:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[IMEC, Synopsys to boost 3D stacked IC development ]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=7e3fab26b5f2dd7dcc56b579e21f8783]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223300028?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[IMEC (Leuven, Belgium) said it is using Synopsys' TCAD simulation tools for characterizing and optimizing the reliability and electrical performance of through-silicon vias (TSVs).<br clear="both" style="clear: both;"/>
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			<pubDate>Tue, 9 Mar 2010 09:39:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Tue, 9 Mar 2010 09:39:00 EST</pubDate>
		</item>
		<item>
			<title><![CDATA[Visitors up 16% at Embedded World]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=7e8a0a9b13cf1d6059a8b03c1757e592]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223300025?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[The organizers of the  Embedded World exhibition and conference 2010 have reported it ended on a very successful note with a record number of visitors and exhibitors, as confirmed by 730 international exhibiting companies, 4 per cent up on last year, and 18,350 trade visitors up 16 per cent. <br clear="both" style="clear: both;"/>
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			<pubDate>Tue, 9 Mar 2010 08:39:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Jim Hogan joins GateRocket advisory board]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=561c883a5bf90fadbf03210ad88741dd]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223300007?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[FPGA verification and debug software vendor GateRocket Inc. announced veteran EDA investor Jim Hogan has joined its advisory board. <br clear="both" style="clear: both;"/>
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			<pubDate>Tue, 9 Mar 2010 04:46:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Getting disciplined about embedded software development: Part 2 - The Seven Step Plan]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=67d5b71ac5db6528613ce0f0d2dd34ce]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223300006?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Here's a guide from Jack Ganssle on doing software development in a disciplined way to reduce both errors and the time it takes to complete a project. Part 2: The Seven Step Plan.<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Tue, 9 Mar 2010 00:47:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Tue, 9 Mar 2010 00:47:00 EST</pubDate>
		</item>
		<item>
			<title><![CDATA[Getting disciplined about embedded software development: Part 1 - Any idiot can write code]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=6d2bf595dc082168f3af4d14956d0589]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223300005?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Here's a guide from Jack Ganssle on doing software development in a disciplined way to reduce both errors and the time it takes to complete a project. Part 1: Any idiot can write code.<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Mon, 8 Mar 2010 13:16:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Carbon readies virtual models for ARM Mali GPUs]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=b8ac95ccb5a03805b2901cfa0b5fc5b6]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223200077?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Carbon Design Systems (Acton, Mass.) has released virtual models for ARM Mali Graphic Processor Units (GPUs). <br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Mon, 8 Mar 2010 09:41:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Ensuring the thermal integrity of your IC package/PC board design]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=0feaed9dd75554f25f4a5b120964507b]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223200064?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Some basic tests will verify your PCB/IC thermal modeling and reality<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Mon, 8 Mar 2010 06:00:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Mon, 8 Mar 2010 06:00:00 EST</pubDate>
		</item>
		<item>
			<title><![CDATA[IMEC, Altos team on chip design, prototyping services ]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=effc626a040af3760d501cc3b9e73e47]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223200057?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[IMEC (Leuven, Belgium) and Altos Design Automation Inc. (San Jose, Calif.) have joined forces to provide offer re-characterization of standard foundry or library vendor libraries including core and IO cells at different process, temperatures and/or voltages.
<br clear="both" style="clear: both;"/>
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			<pubDate>Mon, 8 Mar 2010 05:13:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Decompiling the ARM architecture code]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=4aaf455c7a0cf6d5c26784db1380ff81]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223200134?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[At UBM TechInsights we are often tasked with proving patent infringement of a software algorithm as part of our IP Management Services. Our example algorithm is based on the ARM architecture.<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Mon, 8 Mar 2010 00:01:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Mon, 8 Mar 2010 00:01:00 EST</pubDate>
		</item>
		<item>
			<title><![CDATA[Ag0 targets analog/RF with new circuit optimization tool]]></title>
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			<pheedo:origLink>http://www.edadesignline.com/223200061?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[AgO's AnXplorer simulation- or equation-based optimization tool accelerates device sizing and centers circuit across corners to improve device yield<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Sun, 7 Mar 2010 22:39:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Sun, 7 Mar 2010 22:39:00 EST</pubDate>
		</item>
		<item>
			<title><![CDATA[Undo updates its Linux reversible debugger ]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=a79ab7be0125a722d2640288c1831cfc]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223200063?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[The UndoDB reversible debugger lets developers step or run their application backwards, enabling them to work through code sequences to determine where errors occurred.<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Sun, 7 Mar 2010 15:31:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Chip market to see 'modest' 2010 recovery, says iSuppli]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=0ce32281d070470420d86047c06d69d8]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223300012?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Global semiconductor revenue in 2010 is set to amount to $279.7 billion, a rise of 21.5 percent from $230 million in 2009, according to market research company iSuppli Corp. (El Segundo, Calif.).<br clear="both" style="clear: both;"/>
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			<pubDate>Fri, 5 Mar 2010 09:16:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Fri, 5 Mar 2010 09:16:00 EST</pubDate>
		</item>
		<item>
			<title><![CDATA[A silicon-proven interoperable PDK]]></title>
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			<description><![CDATA[In 2009, TSMC announced the availability of the industry's first interoperable process design kit (iPDK). An iPDK benefits the entire TSMC design chain. TSMC customers will be able to use one unified iPDK to provide advanced functionality across multiple EDA vendor tools, improve design accuracy, shorten design cycle times, and promote design reuse.<br clear="both" style="clear: both;"/>
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			<pubDate>Fri, 5 Mar 2010 08:27:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Fri, 5 Mar 2010 08:27:00 EST</pubDate>
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			<title><![CDATA[Forte enhances ex-Arithmatica's CellMath Designer ]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=21f19b0d9437c79c9b54effc5488d8f1]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223101647?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[High-level synthesis EDA vendor Forte Design Systems has started to ship the latest version of its CellMath Designer datapath synthesis and CellMath IP software. <br clear="both" style="clear: both;"/>
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			<pubDate>Fri, 5 Mar 2010 04:27:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[The MathWorks automates industrial programmable control]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=2a7ccdc00927c39b6bc0b9e4f48f1d1f]]></link>
			<pheedo:origLink>http://www.edadesignline.com/223101644?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[The MathWorks has introduced Simulink PLC Coder for industrial control engineers to automatically generate IEC 61131 structured text for programmable controller devices. <br clear="both" style="clear: both;"/>
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			<pubDate>Fri, 5 Mar 2010 01:15:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Fri, 5 Mar 2010 01:15:00 EST</pubDate>
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