EDA DesignLine

EDA DesignLine http://www.edadesignline.com/ en-us Copyright © 2008 TechInsights, a Division of United Business Media LLC. All rights reserved. bbrosoka@cmp.com http://i.cmpnet.com/edadesignline/EDADesignLine-104x25.jpg EDA DesignLine http://www.edadesignline.com/ 104 25 <![CDATA[The democratization of MEMS design and manufacturing]]> http://www.edadesignline.com/225702659?cid=RSSfeed_EDAdesignline_edadlALL

Semiconductor - Technology - Manufacturing - Microelectromechanical systems - Business]]> Thu, 8 Jul 2010 10:09:00 EDT EDA DesignLine <![CDATA[Presented By:]]> http://ads.pheedo.com/click.phdo?s=6e71c9a48707b3d51ee319a5f0296ab1&p=4 6e71c9a48707b3d51ee319a5f0296ab1

]]> Thu, 8 Jul 2010 10:09:00 EDT <![CDATA[Modernizing the peer code review process]]> http://www.edadesignline.com/225702497?cid=RSSfeed_EDAdesignline_edadlALL

Code review - Software development - Programming - Manufacturing - Software engineering]]> Tue, 6 Jul 2010 15:50:00 EDT EDA DesignLine <![CDATA[Calibre xACT 3D—No compromise extraction for advanced transistor level design]]> http://www.edadesignline.com/225702372?cid=RSSfeed_EDAdesignline_edadlALL

Level design - Business - Materials - Pulp and Paper - Game mechanics]]> Tue, 6 Jul 2010 10:48:00 EDT EDA DesignLine <![CDATA[AWR presents AWR Connected for Cadence Allegro]]> http://www.edadesignline.com/225702358?cid=RSSfeed_EDAdesignline_edadlALL

Printed circuit board - Electronics - Electronic design automation - Technology - Design]]> Tue, 6 Jul 2010 10:03:00 EDT EDA DesignLine <![CDATA[Presented By:]]> http://ads.pheedo.com/click.phdo?s=50487c891c9a7a40fe7bf49520fb8cd8&p=4 50487c891c9a7a40fe7bf49520fb8cd8

]]> Tue, 6 Jul 2010 10:03:00 EDT <![CDATA[TSMC uses Berkeley's FastSpice for device noise analysis]]> http://www.edadesignline.com/225702348?cid=RSSfeed_EDAdesignline_edadlALL

Berkeley Design Automation - Integrated circuit - Electronics - TSMC - Semiconductor]]> Tue, 6 Jul 2010 08:17:00 EDT EDA DesignLine <![CDATA[Altium expands presence in Austria ]]> http://www.edadesignline.com/225702370?cid=RSSfeed_EDAdesignline_edadlALL

Product lifecycle management - CAD and CAM - Data management - Product Data Management - Australia]]> Tue, 6 Jul 2010 07:43:00 EDT EDA DesignLine <![CDATA[Presented By:]]> http://ads.pheedo.com/click.phdo?s=423d860c96e70f6ae4b04470533c50e8&p=4 423d860c96e70f6ae4b04470533c50e8

]]> Tue, 6 Jul 2010 07:43:00 EDT <![CDATA[LabVIEW comes in handy for logic analyzer design]]> http://www.edadesignline.com/225702379?cid=RSSfeed_EDAdesignline_edadlALL

LabVIEW - National Instruments - Programming - Languages - Logic analyzer]]> Tue, 6 Jul 2010 06:22:00 EDT EDA DesignLine <![CDATA[Presented By:]]> http://ads.pheedo.com/click.phdo?s=93028751e8a46d4d7bf5a3849cd683d5&p=4 93028751e8a46d4d7bf5a3849cd683d5

]]> Tue, 6 Jul 2010 06:22:00 EDT <![CDATA[Logic analyzer developed in 10 hours]]> http://www.edadesignline.com/225702342?cid=RSSfeed_EDAdesignline_edadlALL

Field-programmable gate array - Hardware - Programmable Logic - FPGA - Math]]> Tue, 6 Jul 2010 05:56:00 EDT EDA DesignLine <![CDATA[Presented By:]]> http://ads.pheedo.com/click.phdo?s=1acd84c1272023e9f5d1d123cbefefb7&p=4 1acd84c1272023e9f5d1d123cbefefb7

]]> Tue, 6 Jul 2010 05:56:00 EDT <![CDATA[Calibre Pattern Matching: Picture It Match It... Done!]]> http://www.edadesignline.com/225702335?cid=RSSfeed_EDAdesignline_edadlALL

Pattern matching - Programming - Patterns - Crafts - Business]]> Tue, 6 Jul 2010 04:36:00 EDT EDA DesignLine <![CDATA[Presented By:]]> http://ads.pheedo.com/click.phdo?s=939fde4e834392628d0c1a79c9f91538&p=4 939fde4e834392628d0c1a79c9f91538

]]> Tue, 6 Jul 2010 04:36:00 EDT <![CDATA[SPICE Simulation of Transmission Lines by the Telegrapher's Method (Part 2 of 3)]]> http://www.edadesignline.com/225702310?cid=RSSfeed_EDAdesignline_edadlALL

SPICE - Frequency - Transmission line - Technology - Simulation]]> Mon, 5 Jul 2010 06:30:00 EDT EDA DesignLine <![CDATA[Fundamental challenges of PCB assembly and test]]> http://www.edadesignline.com/225702308?cid=RSSfeed_EDAdesignline_edadlALL

Printed circuit board - Electronics - Manufacturing - Mentor Graphics - Business]]> Mon, 5 Jul 2010 05:46:00 EDT EDA DesignLine <![CDATA[Presented By:]]> http://ads.pheedo.com/click.phdo?s=738dc86be99f829de417f73cfef1ae4e&p=4 738dc86be99f829de417f73cfef1ae4e

]]> Mon, 5 Jul 2010 05:46:00 EDT <![CDATA[OVM guidelines]]> http://www.edadesignline.com/225702307?cid=RSSfeed_EDAdesignline_edadlALL

SystemVerilog - Library - Methodology - Social Sciences - Libraries]]> Mon, 5 Jul 2010 05:10:00 EDT EDA DesignLine <![CDATA[Professional PCB design tool comes for free]]> http://www.edadesignline.com/225702361?cid=RSSfeed_EDAdesignline_edadlALL

Printed circuit board - Electronics - Technology - Electronic design automation - Design]]> Mon, 5 Jul 2010 04:57:00 EDT EDA DesignLine <![CDATA[The analog IC "shortage": real or hype?]]> http://www.edadesignline.com/225702375?cid=RSSfeed_EDAdesignline_edadlALL

Integrated circuit - Business - Electronics and Electrical - Components - Semiconductors]]> Sun, 4 Jul 2010 14:55:46 EDT EDA DesignLine <![CDATA[Presented By:]]> http://ads.pheedo.com/click.phdo?s=5c01ef19390c9b1013b68511ee31fdd9&p=4 5c01ef19390c9b1013b68511ee31fdd9

]]> Sun, 4 Jul 2010 14:55:46 EDT <![CDATA[VeriLogger environment available with free 6 month license]]> http://www.edadesignline.com/225702338?cid=RSSfeed_EDAdesignline_edadlALL

Altera - Actel - Xilinx - Verilog - Design]]> Fri, 2 Jul 2010 04:43:00 EDT EDA DesignLine <![CDATA[Code testing process more accessible for developers]]> http://www.edadesignline.com/225702377?cid=RSSfeed_EDAdesignline_edadlALL

Unit Test - Israel - Typemock - Software testing - Programming]]> Thu, 1 Jul 2010 11:43:00 EDT EDA DesignLine <![CDATA[How productive is your R&D organization?]]> http://www.edadesignline.com/225701954?cid=RSSfeed_EDAdesignline_edadlALL

Engineering - Business - RESEARCH AND DEVELOPMENT - Industrial Goods and Services - Productivity]]> Thu, 1 Jul 2010 10:22:00 EDT EDA DesignLine <![CDATA[Presented By:]]> http://ads.pheedo.com/click.phdo?s=1389654612a1c4d64d272dbb63c233fc&p=4 1389654612a1c4d64d272dbb63c233fc

]]> Thu, 1 Jul 2010 10:22:00 EDT <![CDATA[The Inefficiency of C++, Fact or Fiction? ]]> http://www.edadesignline.com/225701912?cid=RSSfeed_EDAdesignline_edadlALL

Language - Code bloat - C++ - Arts - Social Sciences]]> Wed, 30 Jun 2010 10:09:00 EDT EDA DesignLine <![CDATA[FPGA Virtual Conference archives now available]]> http://www.edadesignline.com/225701878?cid=RSSfeed_EDAdesignline_edadlALL

Field-programmable gate array - Hardware - Programmable Logic - FPGA - Consultants]]> Tue, 29 Jun 2010 13:11:00 EDT EDA DesignLine <![CDATA[Presented By:]]> http://ads.pheedo.com/click.phdo?s=7f5075f1bae14ecda8d33c84f6dc2c84&p=4 7f5075f1bae14ecda8d33c84f6dc2c84

]]> Tue, 29 Jun 2010 13:11:00 EDT <![CDATA[Dolphin Integration rolls panoply of IPs to reduce 65nm silicon area ]]> http://www.edadesignline.com/225701762?cid=RSSfeed_EDAdesignline_edadlALL

Electronic design automation - Intellectual property - Business - Separation of concerns - Components]]> Tue, 29 Jun 2010 10:05:00 EDT EDA DesignLine <![CDATA[Making the most of the system level in analog design]]> http://www.edadesignline.com/225701753?cid=RSSfeed_EDAdesignline_edadlALL

Technology - Spice - Electronic design automation - Business - Level]]> Tue, 29 Jun 2010 08:44:00 EDT EDA DesignLine <![CDATA[Presented By:]]> http://ads.pheedo.com/click.phdo?s=cffdb0337bd95980723e0760079b4dcc&p=4 cffdb0337bd95980723e0760079b4dcc

]]> Tue, 29 Jun 2010 08:44:00 EDT <![CDATA[Using FPGA prototyping board as an SoC verification and integration platform]]> http://www.edadesignline.com/225701738?cid=RSSfeed_EDAdesignline_edadlALL

Field-programmable gate array - Hardware - System-on-a-chip - Programmable Logic - FPGA]]> Tue, 29 Jun 2010 05:03:00 EDT EDA DesignLine <![CDATA[Green Hills supports Freescale's 64-bit e5500 and 3 QorIQ comms processors]]> http://www.edadesignline.com/225701744?cid=RSSfeed_EDAdesignline_edadlALL

Freescale Semiconductor - QorIQ - Hardware - Components - Operating system]]> Mon, 28 Jun 2010 17:02:00 EDT EDA DesignLine <![CDATA[Presented By:]]> http://ads.pheedo.com/click.phdo?s=836ea7486e61b416b477cc47b3660885&p=4 836ea7486e61b416b477cc47b3660885

]]> Mon, 28 Jun 2010 17:02:00 EDT <![CDATA[SPICE Simulation of Transmission Lines by the Telegrapher's Method (Part 1 of 3)]]> http://www.edadesignline.com/225701737?cid=RSSfeed_EDAdesignline_edadlALL

SPICE - Frequency - Transmission line - Technology - Simulation]]> Mon, 28 Jun 2010 06:30:00 EDT EDA DesignLine <![CDATA[Presented By:]]> http://ads.pheedo.com/click.phdo?s=e2e086e45e96a017ad07cb82805137d9&p=4 e2e086e45e96a017ad07cb82805137d9

]]> Mon, 28 Jun 2010 06:30:00 EDT <![CDATA[Lattice revamps design tools to ease FPGAs use]]> http://www.edadesignline.com/225701751?cid=RSSfeed_EDAdesignline_edadlALL

Field-programmable gate array - Lattice Semiconductor - Hardware - Programmable Logic - FPGA]]> Mon, 28 Jun 2010 02:24:00 EDT EDA DesignLine