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		<title>EDA DesignLine</title>
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			<title><![CDATA[Altium adds Altera Cyclone III to NanoBoard club]]></title>
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			<description><![CDATA[Altium has expanded its NanoBoard 3000 platform with a board  hosting an Altera Cyclone III FPGA.<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Tue, 9 Feb 2010 05:19:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Tue, 9 Feb 2010 05:19:00 EST</pubDate>
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		<item>
			<title><![CDATA[Reducing Costs, Risks, Time to Market with Virtualized Systems Development]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=3d196729eb223182f0f4f1485fe7bd18]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222700451?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[To achieve developer efficiency and software quality with virtual system development tools, it is necessary to use a fully-featured simulation infrastructure with the ability to create custom models.<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Mon, 8 Feb 2010 20:54:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[Synopsys to acquire ESL vendor CoWare]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=252b743d991e0657157b03139b394c7e]]></link>
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			<description><![CDATA[EDA and IP vendor Synopsys announced its second major acquisition in two weeks, saying it signed a definitive agreement to acquire electronic system-level design software vendor Coware. Financial terms of the agreement were not disclosed.<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Mon, 8 Feb 2010 17:01:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[Hardware Testing]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=70a94842480991403888b13f9ed96feb]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222700450?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Board testing is harder than you think, but there are solutions<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Mon, 8 Feb 2010 13:59:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[Time domain modeling and simulation of Intel QuickPath interconnect circuits (Part 1 of 3)]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=62a21a3afa023564e28fe4c100d28482]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222700452?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[This article explores and explains key issues related to modeling and simulation in this interconnect scheme, but its lessons apply to other designs as well<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Mon, 8 Feb 2010 06:00:17 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Mon, 8 Feb 2010 06:00:17 EST</pubDate>
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			<title><![CDATA[An analyst's 10 reasons to be cheerful]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=a4735751cf6271797f3784ddeb46ca73]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222700225?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Bill McClean, analyst with IC Insights Inc. (Scottsdale, Ariz.) has provided ten reasons that support the idea that 2010 could be between a good and a great year for the semiconductor industry. <br clear="both" style="clear: both;"/>
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			<pubDate>Mon, 8 Feb 2010 05:27:00 EST</pubDate>
			<category>EDA DesignLine</category>
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		<item>
			<title><![CDATA[Verdi power-aware debug module enables visualization of power intent]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=ee063d97156b5b5d5e91e7bef5a19430]]></link>
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			<description><![CDATA[SpringSoft introduced a new power-aware debug module for its Verdi automated debug system, accelerating the comprehension of power intent and automating the process of visualizing, tracing and analyzing the source of power-related errors<br clear="both" style="clear: both;"/>
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			<pubDate>Mon, 8 Feb 2010 03:31:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[New CEO Sandeep Vij forms 'Team MIPS']]></title>
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			<description><![CDATA[Signing Sandeep Vij as its new CEO may turn out to be just what MIPS Technologies needed, as the world's number two processor IP company struggles to steal the spotlight back from ARM -- both in media attention and the industry's mindshare.<br clear="both" style="clear: both;"/>
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			<pubDate>Sun, 7 Feb 2010 18:13:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Sun, 7 Feb 2010 18:13:00 EST</pubDate>
		</item>
		<item>
			<title><![CDATA["Also of Interest" and "Elementals" for February 8, 2010; plus recent "Planet Analog" Newsletters]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=827ec8400eabbb4dbdb8d8c64fa8038c]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222700206?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Check out these interesting and tutorial items from other engineering and design publications, as well as an archive of the &quot;Planet Analog&quot; Newsletter<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Sat, 6 Feb 2010 12:00:06 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Making packet processing more efficient with network-optimized multicore designs: Part 2]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=1297b2eabaadd709f55ccb373a659dc3]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222700219?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[In terms of both power consumption, it is now feasible to build complete network packet processing designs using general purpose architecture processors, rather than dedicated ASIC and ASSP SoCs optimized for the application. Part 2: Minimizing/hiding latency.<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Fri, 5 Feb 2010 21:09:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Fri, 5 Feb 2010 21:09:00 EST</pubDate>
		</item>
		<item>
			<title><![CDATA[RTS Hypervisor V2.2 enables MSI support for all operating systems]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=d1901c1b69c37278f8259d9b62926135]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222700216?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[<br clear="both" style="clear: both;"/>
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			<pubDate>Fri, 5 Feb 2010 18:12:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Managing Complex SoC verification using plan based verification techniques]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=56f552fe849c130a68e6b011c6d73569]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222700069?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Meeting the quality requirements of a complex SoC requires managing large verification projects. In this article, Freescale and STMicroelectronics recount a recent experience with a verification management solution (Incisive Enterprise Manager) from Cadence, for the verification of a 32-bit microcontroller project for the automotive industry.<br clear="both" style="clear: both;"/>
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			<pubDate>Fri, 5 Feb 2010 10:31:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[HARDWARE TOOLS: Preconfigured OpenVPX development systems speed design]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=4ed3ea469f47717d3bdc188e9a86639e]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222700051?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Concurrent Technologies (Colchester, UK) has developed two off the shelf, 3U OpenVPX development systems to complement its growing OpenVPX family of boards. <br clear="both" style="clear: both;"/>
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			<pubDate>Fri, 5 Feb 2010 04:55:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Cadence back in black in Q4]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=2c817ce6fa780b68f8f862fbc33aa74e]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222700021?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[EDA vendor Cadence Design Systems Inc. (San Jose, Calif.) reported a net income of $2 million, based on generally accepted accounting principles (GAAP), for the fourth quarter of 2009, compared to a net loss of $1.63 billion a year ago. <br clear="both" style="clear: both;"/>
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			<pubDate>Fri, 5 Feb 2010 02:55:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Researchers propose commonsense plan to improve verification process]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=3d4612cc1cc2e6ba8d5087730ca5514e]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222700052?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Researchers have proposed an integrated, all-encompassing plan for verification teams based on a commonsense approach and proper documentation of all aspects of the process<br clear="both" style="clear: both;"/>
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			<pubDate>Fri, 5 Feb 2010 01:13:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Fri, 5 Feb 2010 01:13:00 EST</pubDate>
		</item>
		<item>
			<title><![CDATA[Layering it on--a new approach to automating system tests ]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=ac067489ee12e25c58bfd453d24af88a]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222700022?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Here's a layered approach to testing that uses pluggable software components to assure scalability and portability. <br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Fri, 5 Feb 2010 00:00:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Universities gain access to Agilent, EVE, Altium, Evatronix tools ]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=e106cf423fecacec0ead877f26ddcb0c]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222601153?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[This week, EDA companies EVE SA, Agilent Technologies Inc., Altium Ltd. and Evatronix SA have either signed sales contracts or collaboration agreements to provide global universities with their tools. <br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Thu, 4 Feb 2010 11:07:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Thu, 4 Feb 2010 11:07:00 EST</pubDate>
		</item>
		<item>
			<title><![CDATA[Virage Logic posts strong growth ]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=0806ea369f8fc0b4a7e8194bc126bc0f]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222601105?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Virage Logic Corp. posted sales of $21.7 million for the first quarter of fiscal year 2010, ended Dec. 31, 2009, up from $11.3 million a year ago. <br clear="both" style="clear: both;"/>
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			<pubDate>Thu, 4 Feb 2010 06:33:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[DRAM leads top ten IC growth sectors for 2010, says analyst]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=c42f877e1a9eed0f371a8a5530f0ad1a]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222601107?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[All but four of about 28 IC product categories will grow in 2010 resulting in an overall IC market growth of 15 percent, according to a forecast from market research firm IC Insights Inc. (Scottsdale, Ariz.).<br clear="both" style="clear: both;"/>
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			<pubDate>Thu, 4 Feb 2010 05:44:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[NEWS: Restructuring starts to pay dividends for Enea]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=38b8b466c18984fcbf4de6a2d911f081]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222601094?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[A year that has been characterized by cost cutting and restructuring programs has seen Enea (Stockholm, Sweden) report its year-end results with net sales falling by 15 percent, mainly due to reduced royalties from telecom customers and a downturn in the demand for consultancy services.<br clear="both" style="clear: both;"/>
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			<pubDate>Thu, 4 Feb 2010 04:04:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Presented By:]]></title>
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			<pubDate>Thu, 4 Feb 2010 04:04:00 EST</pubDate>
		</item>
		<item>
			<title><![CDATA[Macraigor extends on-chip debug support to Intel's Atom]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=8a0acff956bd263b543ad76965a4cbc8]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222601089?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[OCDemon technology is being offered for kernel debugging and low-level driver development on Atom platforms<br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Thu, 4 Feb 2010 00:42:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[Lifecycle development comes to complex critical software projects]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=71ce06ac4ab25fa43bb5c204c181ab71]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222600911?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[LDRA (Wirral, UK), and Visure Solutions (Madrid, Spain), have cooperated to provide an end-to-end application lifecycle management (ALM) system for the embedded space. <br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 3 Feb 2010 04:59:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[When good compilers go bad, or What you see is not what you execute]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=13501d1b40b2206310d8c334e6b59e1a]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222600904?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[Getting rid of the mismatch between source code and compiled machine code may mean having to debug the machine code. Here's some of the latest research on finding a tool to combat the problem. <br clear="both" style="clear: both;"/>
<br clear="both" style="clear: both;"/>
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			<pubDate>Wed, 3 Feb 2010 00:00:00 EST</pubDate>
			<category>EDA DesignLine</category>
		</item>
		<item>
			<title><![CDATA[The basics of clock jitter in embedded system designs]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=613998c9e91619126ae22047ef29fbca]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222600924?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[With the increasing system data rates, timing jitter has become critical in system design, especially where system performance limit is determined by the system timing margin, making it important to understand the impact of timing jitter. <br clear="both" style="clear: both;"/>
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			<pubDate>Tue, 2 Feb 2010 20:52:00 EST</pubDate>
			<category>EDA DesignLine</category>
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			<title><![CDATA[Synopsys buys virtual system prototyping provider]]></title>
			<link><![CDATA[http://www.pheedcontent.com/click.phdo?i=6fbd0f7b6eb268d1cbbb7bf3d3a7a2a1]]></link>
			<pheedo:origLink>http://www.edadesignline.com/222600900?cid=RSSfeed_EDAdesignline_edadlALL</pheedo:origLink>
			<description><![CDATA[EDA and IP vendor Synopsys has acquired virtual system prototyping technology provider Vast Systems  Technology. Financial terms of the deal were not disclosed. <br clear="both" style="clear: both;"/>
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			<pubDate>Tue, 2 Feb 2010 18:35:00 EST</pubDate>
			<category>EDA DesignLine</category>
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